Using Matlab to generate a VHDL ASCII to Binary transcoder

ASCII character aren't so easy to manipulate in VHDL. In fact I started to use it as a native type of VHDL but in using QUARTUS VHDL compiler we can't output character. We can't build entity with "complex type" outputs or inputs. I try to cast "character" to "std_logic_vector" but we can't do it with "std_logic_1164.all", "std_logic_unsigned.all", "std_logic_arith.all" and "numeric_std.all" ieee library.

I saw this 'quick&very dirty way' solution wich enable to create you own library. I find the idea good but the code is limited to a small amount of characters and its quite tiresome to add the other characters.

Here is a small Matlab script to generate the "case" structure with the whole ASCII characters.

FileID = fopen('transcoderASCII2Binary.h','w');

fprintf(FileID, '\t\tcase char is\n');

for i=32:127
fprintf(FileID, '\t\t when ''%s''=> \n\t\t\t data <= "%s"; \n',char(i), dec2bin(i,8)); end fprintf(FileID, '\t\t when others => \n\t\t\t data <= "00000000"; \n'); fprintf(FileID, 'end case;'); fclose(FileID); And here is the result :


case char is
when ' '=>
data <= "00100000";
when '!'=>
data <= "00100001";
when '"'=>
data <= "00100010";
when '#'=>
data <= "00100011";
when '$'=>
data <= "00100100";
[............]
when '~'=>
data <= "01111110";
when ''=>
data <= "01111111";
when others =>
data <= "00000000";
end case;